As Integrated Circuit (“IC”) devices are becoming more complex, the cost of testing has escalated to a level where it is creating concern in the industry both in terms of technology limitations and the cost of testing. As a result, there is a continual effort to reduce the total cost of test devices. These initiatives are further fuelled by the continuing drive to reduce the cost of components. Hence elimination of any wastage overheads from testing and packaging has gained significant attention in recent years, and will continue to play a major role. Industry and market data shows that the operation and maintenance of test equipment contributes a major portion to the overall test cost.
Current solutions in place and proposed each have technological limitations. Integrated Circuits are tested (i.e.: Device Under Test [“DUT”]) typically one at a time by transmitting test data between the test controller and the test head. Multiple touchdowns are performed to test a complete wafer. Due to the distance a signal traverses, there is degradation of signals along with potential noise interference. Multiple channel solutions for testing multiple devices in parallel are costly to implement and possess further reliability issues due to poor signal integrity or potential cross-talk interference. As a consequence of these higher test costs and reliability issues, solutions for parallel test are limited in parallelism (number of sites). Further, adoption has generally been limited to niche markets such as memory test.
The nature of high speed and mixed signal measurements has meant that cost effective wafer test of high speed devices has been difficult to obtain. One of the most effective ways of reducing wafer test costs is higher test parallelism. Note that these issues are true whether measuring wafers, ICs, packaged devices, or even Strips or aggregations of packaged devices. However, prior art devices either are not capable of a high level of parallelism or can do so only at great expense.
Signal integrity issues, costly high speed instrumentation and complex probe card architectures all work against high parallel high speed wafer testing. Today high speed devices are typically tested in either single site or possibly ×2 parallelism. Alternately, some manufacturers opt to perform only DC or low frequency measurements at wafer level for their high speed devices, causing unacceptably high package yield loss. High speed testing includes RF or Memory or serial wired testing.
A growing industry trend has seen the procurement lead times for advanced probe cards that facilitate multi-site testing increase dramatically. This presents a major problem for industry since these lead times can add significant time in the design to manufacture cycle of an integrated circuit design and thus become a significant factor in the time to market for a new chip design.
Prior art probe cards typically have a rigid architecture in which each probe is positioned so as to contact a specific site on a device under test (DUT). The probes may be coupled to an integrated circuit (IC) so that signals between automated test equipment (ATE) and the DUT via the probes are conditioned or otherwise processed for transmission, as described by Rutten in U.S. Pat. No. 6,747,469. The limitation of this technique is that the solution is not cost effective because different designs of DUT chips require a different design of the pre-conditioning IC (“PCIC”) leading to unacceptably high non-recurring engineering (“NRE”) costs.
The PCIC described by Rutten must be customized by final fabrication steps in the IC process. This customization is the final metal interconnects layers of an IC fabrication, which requires a large investment in design, tooling, capital and know-how. This also fixes the utility of the PCIC and restricts its use to specific DUT designs and specific DUT applications.
In addition, the contact points in Rutten must be customized to physically match both the DUT pads as well as the PCIC. This ‘mirror’ image contact concept places a burden on the economics of implementation as it requires specific and detailed a-priori knowledge of the DUT before the PCIC is contemplated or constructed leading to unacceptably long lead times to procure a probe card due to the need to procure a custom integrated circuit.
Finally, the Rutten embodiments are susceptible to unacceptably high failure rates of the PCIC due to electronic failure of the PCIC as a result of die cracks and other stress induced failure modes due to mechanical stresses of probes placed over active areas of the PCIC.
The United States Patent 20050237073 A1 describes a method of testing a DUT using a programmable FPGA circuit board that is located on a probe card. This apparatus employs a circuit board and IC's on the probe card to distribute signals. No processing is done to analyse high-speed signals and convert to low-speed for eliminating high frequency resource requirements on the tester.
Harame et al. in IBM Journal of Research and Development, Vol. 47, No. 2/3 dated March/May 2003, pages 139-175, describe the need for integrity in complex RF and mixed-signal communications in “Design automation methodology and RF/analog modeling for RF CMOS and SiGe BiCMOS technologies.” They show that the rapidly expanding market for electronic components has led to demand for more rapid testing without incurring high costs, with high reliability and minimum distortion of test signals and responses. These circuits are for implementation on a PCB positioned on a load board used for testing packaged components, not on semiconductor devices for testing devices in wafer form and therefore signal transmission and degradation issues through PCB still exist.